1. Field of the Invention
This invention relates to a method of manufacturing a semiconductor device, and in particular, to a method of manufacturing a high-speed semiconductor device such as a high-speed logic LSI, a system LSI, a memory/logic hybrid LSI, etc.
2. Description of the Related Art
In recent years, there has been proposed to decrease the relative dielectric constant of an interlayer insulating film to 3.0 or less by using a monolayer or multi-layer organic film or an organic/inorganic hybrid film in an attempt to minimize the wiring resistance and inter-wiring capacity of metallic wiring in a semiconductor integrated circuit.
A dual damascene structure using a hybrid film can be fabricated by a dual hard mask method or a triple hard mask method wherein plural hard masks are employed. In these working processes, a trench pattern is formed on an upper hard mask, which is followed by a lithography process for forming a pattern of holes. On this occasion, due to step portions of the hard mask, non-uniformity in film thickness occurs in a resist film. More specifically, the thickness of the resist film formed over a wiring having a relatively large width of the order of several microns to several tens of microns would become inevitably thinner as compared with the thickness of the resist film formed over a fine wiring having a width of the order of several tens microns to several hundreds of microns.
Such a difference in film thickness of the resist film would lead to a generation of focus error at the exposure, thus generates non-uniformity of the dimension of wiring, resulting in the deterioration in yield of wiring. On the occasion of forming a pattern on an underlying layer accompanying such a step portion, a multilayer resist method is frequently employed. With a recent trend to further refine a pattern, it is imperative to further decrease the thickness of the underlying layer in order to secure the resolution of the pattern. As a result, it is very difficult to alleviate the non-uniformity in thickness of the resist film, which has been caused to occur due to the step portion of the hard mask.
With regard to the process of forming wiring trenches and interconnecting holes by using plural layers of hard masks, there has been proposed a method wherein an underlying layer is deposited immediately above a second mask layer having a pattern of wiring trenches formed thereon, and then the surface of this underlying layer is planarized. In this case, this underlying layer is formed of a silicon oxide film, and the base layer on which this underlying layer is deposited is also constituted by a silicon oxide film. Therefore, it is possible to remove this underlying layer when etching the silicon oxide film constituting the base layer without necessitating a separate process which is exclusively assigned for the removal of this underlying layer. However, in order to protect the second mask layer existing immediately below this underlying layer, this underlying layer is required to be formed so as to sufficiently cover this second mask layer. When these circumstances are taken into account, this underlying layer is required to have more or less a sufficient degree of thickness, thus limiting the thinning of this underlying layer.